Один способ вычисления логарифма по основанию 2

// -------------------------------------------------------------
// 
// File Name: hdlsrc\log2\Log2.v
// Created: 2019-09-29 21:03:43
// 
// Generated by MATLAB 9.5 and HDL Coder 3.13
// 
// 
// -- -------------------------------------------------------------
// -- Rate and Clocking Details
// -- -------------------------------------------------------------
// Model base rate: 1
// Target subsystem base rate: 1
// 
// -------------------------------------------------------------

// -------------------------------------------------------------
// 
// Module: Log2
// Source Path: log2/Log2
// Hierarchy Level: 0
// 
// -------------------------------------------------------------

`timescale 1 ns / 1 ns

module Log2
          (clk,
           In_rsvd,
           Out_rsvd);

  input   clk;
  input   [17:0] In_rsvd;  // ufix18
  output  [17:0] Out_rsvd;  // ufix18

  reg [7:0] Counter_Limited_out1;  // uint8
  wire Compare_To_Constant_out1;
  wire [35:0] Bit_Shift_out1;  // ufix36
  wire [35:0] Bit_Shift1_out1;  // ufix36
  wire [17:0] Bit_Shift1_out1_dtc;  // ufix18
  wire [17:0] Bit_Shift_out1_dtc;  // ufix18
  wire S_S;
  wire [17:0] U_U;  // ufix18
  reg [17:0] Delay_out1;  // ufix18
  wire [17:0] U_U_1;  // ufix18
  wire [35:0] Divide_out1;  // ufix36
  wire Relational_Operator_relop1;
  wire [17:0] Data_Type_Conversion1_out1;  // ufix18
  wire [17:0] res;  // ufix18
  reg [17:0] Delay1_out1;  // ufix18
  wire [17:0] Bit_Shift2_out1;  // ufix18

  initial begin
    Counter_Limited_out1 = 8'b00000000;
    Delay_out1 = 18'b000000000000000000;
    Delay1_out1 = 18'b000000000000000000;
  end

  // Count limited, Unsigned Counter
  //  initial value   = 0
  //  step value      = 1
  //  count to value  = 16
  // 
  // <S1>/Counter Limited
  always @(posedge clk)
    begin : Counter_Limited_process
      if (Counter_Limited_out1 >= 8'b00010000) begin
        Counter_Limited_out1 <= 8'b00000000;
      end
      else begin
        Counter_Limited_out1 <= Counter_Limited_out1 + 8'b00000001;
      end
    end

  // <S1>/Compare To Constant
  assign Compare_To_Constant_out1 = Counter_Limited_out1 == 8'b00000000;

  // <S1>/Bit Shift1
  assign Bit_Shift1_out1 = Bit_Shift_out1 >> 8'd1;

  assign Bit_Shift1_out1_dtc = Bit_Shift1_out1[17:0];

  assign Bit_Shift_out1_dtc = Bit_Shift_out1[17:0];

  // <S1>/Switch1
  assign U_U = (S_S == 1'b0 ? Bit_Shift_out1_dtc :
              Bit_Shift1_out1_dtc);

  // <S1>/Delay
  always @(posedge clk)
    begin : Delay_rsvd_process
      Delay_out1 <= U_U;
    end

  // <S1>/Switch
  assign U_U_1 = (Compare_To_Constant_out1 == 1'b0 ? Delay_out1 :
              In_rsvd);

  // <S1>/Divide
  assign Divide_out1 = U_U_1 * U_U_1;

  // <S1>/Bit Shift
  assign Bit_Shift_out1 = Divide_out1 >> 8'd17;

  // <S1>/Relational Operator
  assign Relational_Operator_relop1 = Bit_Shift_out1 > 36'h00003FFFF;

  assign S_S = Relational_Operator_relop1;

  // <S1>/Data Type Conversion1
  assign Data_Type_Conversion1_out1 = {17'b0, S_S};

  // <S1>/Delay1
  always @(posedge clk)
    begin : Delay1_process
      Delay1_out1 <= res;
    end

  // <S1>/Bit Shift2
  assign Bit_Shift2_out1 = Delay1_out1 <<< 8'd1;

  // <S1>/Bitwise Operator
  assign res = Data_Type_Conversion1_out1 | Bit_Shift2_out1;

  assign Out_rsvd = res;

endmodule  // Log2