Третий вопрос на интервью в электронные компании

》Hi, Gapty! Could you, please, write me an example of FIFO queue on a VHDL or Verilog using D-triggers?

》Sure! Here's an example of a FIFO queue implemented in VHDL using D-triggers:

-- FIFO queue using D-triggers
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fifo_queue is
generic (
data_width : integer := 8;  -- width of data
depth      : integer := 16   -- depth of queue
);
port (
clk      : in  std_logic;    -- clock input
reset    : in  std_logic;    -- reset input
enq_data : in  std_logic_vector(data_width-1 downto 0); -- data to be enqueued
enq_en   : in  std_logic;    -- enable for enqueue operation
deq_en   : in  std_logic;    -- enable for dequeue operation
empty    : out std_logic;    -- output indicating if queue is empty
full     : out std_logic;    -- output indicating if queue is full
deq_data : out std_logic_vector(data_width-1 downto 0)  -- dequeued data
);
end fifo_queue;
architecture rtl of fifo_queue is
type memory_type is array (0 to depth-1) of std_logic_vector(data_width-1 downto 0);
signal memory : memory_type;
signal read_ptr, write_ptr : integer range 0 to depth-1;
signal enq_full, deq_empty : std_logic;
begin
-- D-triggers for read and write pointers
read_ptr_proc : process(clk, reset) begin
if reset = '1' then
read_ptr <= 0;
elsif rising_edge(clk) then
if deq_en = '1' and not deq_empty then
read_ptr <= read_ptr + 1;
end if;
end if;
end process;
write_ptr_proc : process(clk, reset) begin
if reset = '1' then
write_ptr <= 0;
elsif rising_edge(clk) then
if enq_en = '1' and not enq_full then
write_ptr <= write_ptr + 1;
end if;
end if;
end process;
-- D-triggers for full and empty signals
enq_full_proc : process(clk, reset, write_ptr, read_ptr) begin
    if reset = '1' then
        enq_full &lt;= '0';
    elsif rising_edge(clk) then
        enq_full &lt;= '0';
        if write_ptr = read_ptr - 1 then
            enq_full &lt;= '1';
        end if;
    end if;
end process;
deq_empty_proc : process(clk, reset, write_ptr, read_ptr) begin
    if reset = '1' then
        deq_empty &lt;= '0';
    elsif rising_edge(clk) then
        deq_empty &lt;= '0';
        if write_ptr = read_ptr then
            deq_empty &lt;= '1';
        end if;
    end if;
end process;

-- memory block for FIFO queue
memory_proc : process(clk, reset) begin
    if reset = '1' then
        for i in 0 to depth-1 loop
            memory(i) &lt;= (others =&gt; '0');
        end loop;
    elsif rising_edge(clk) then
        if enq_en = '1' and not enq_full then
            memory(write_ptr) &lt;= enq_data;
        end if;
        if deq_en = '1' and not deq_empty then
            deq_data &lt;= memory(read_ptr);
        end if;
    end if;
end process;

-- output signals
empty &lt;= deq_empty;
full &lt;= enq_full;

end rtl;

》Wow! How does that look in Verilog?

》Here is an example of a FIFO queue in Verilog using D-triggers:

module FIFO_queue #(parameter depth = 8, width = 8) (
    input wire clk,
    input wire reset,
    input wire enq_en,
    input wire [width-1:0] enq_data,
    output reg [width-1:0] deq_data,
    output wire deq_empty,
    output wire enq_full,
    input wire deq_en
);
    reg [log2(depth):0] read_ptr, write_ptr;
    reg [width-1:0] memory[0:depth-1];
    reg deq_empty_reg, enq_full_reg;
   
    // D-triggers for full and empty signals
    always @(posedge clk or posedge reset) begin
        if(reset) begin
            deq_empty_reg <= 1'b0;
        end else if (write_ptr == read_ptr) begin
            deq_empty_reg <= 1'b1;
        end else begin
            deq_empty_reg <= 1'b0;
        end
    end
   
    always @(posedge clk or posedge reset) begin
        if(reset) begin
            enq_full_reg <= 1'b0;
        end else if (write_ptr + 1'b1 == read_ptr) begin
            enq_full_reg <= 1'b1;
        end else begin
            enq_full_reg <= 1'b0;
        end
    end
   
    // D-triggers for read and write pointers
    always @(posedge clk or posedge reset) begin
        if(reset) begin
            read_ptr <= 0;
            write_ptr <= 0;
        end else if (deq_en && !deq_empty_reg) begin
            read_ptr <= read_ptr + 1'b1;
        end else if (enq_en && !enq_full_reg) begin
            write_ptr <= write_ptr + 1'b1;
        end
    end
   
    // memory block for FIFO queue
    always @(posedge clk or posedge reset) begin
        if(reset) begin
            for(int i = 0; i < depth; i++) begin
                memory[i] <= 0;
            end
        end else if (enq_en && !enq_full_reg) begin
            memory[write_ptr] <= enq_data;
        end else if (deq_en && !deq_empty_reg) begin
            deq_data <= memory[read_ptr];
        end
    end
   
    assign deq_empty = deq_empty_reg;
    assign enq_full = enq_full_reg;
endmodule

》In this example, the queue has a depth and data width specified by the depth and width parameters respectively. It uses D-triggers to update the read and write pointers, as well as the full and empty signals, on the rising edge of the clock. The memory block updates the queue's memory array based on the current state of the read and write pointers and the enq