Hello, fellow developers!

Anyone who designs multilayer printed circuit boards in KiCad has faced the need, during routing, to leave large areas free of copper polygons (whether connected to nets or not) for schematic or other reasons. On outer layers, this isn't a big problem. On inner layers, it's a bit different. While it might be fine from a topology perspective, it's not ideal from a manufacturing point of view.

Today, we want to share a plugin we developed to solve this problem. It's a tool for automatically filling free areas on a PCB with non-current-carrying copper elements, either square or round, of a configurable size.

Why is this needed?

At first glance, an empty area on a board is just bare laminate without copper. But for the manufacturer and the end-user of the device, this has two important consequences:

1. Cost Savings in Manufacturing (and Benefits for the Environment)

During chemical etching, we remove copper. The more empty spaces there are, the more copper ends up in the etching solution. For small batches, this is negligible, but in large-scale series production, the consumption of chemicals is a significant cost factor. By filling voids with copper, we leave it on the board instead of it ending up in the tank with reagents. The manufacturer benefits, and it's good for the environment.

2. Uniformity of Board Thickness (Stability of Mechanical and Electrical Parameters)

This is critical specifically for multilayer boards. Imagine a "sandwich" of cores and prepreg. If there are huge areas without copper on inner layers, alongside areas densely packed with traces and copper pours, pressure during lamination is distributed unevenly. This results in a board with non-uniform thickness and density, creating risks:

Warpage of the finished board (especially on large formats).
Distortion of the layer structure.
Unstable characteristic impedance, critical for RF circuits.

Uniform filling with copper elements makes the board mechanically stable, thickness uniform, and electrical parameters predictable.

Plugin Features

Copper Filler finds empty areas on a selected layer and fills them with copper circles or squares that are not connected to any net. It's simply "copper" that aids manufacturing but doesn't interfere with circuit operation.

The main "trick" is that the filling isn't done randomly; it respects the technological clearances and minimum sizes specified by the user.

The plugin is multi-threaded, which reduces board processing time.

Each plugin call is accompanied by a logger call. It might be disabled in future versions, but it will remind you of itself with each execution.

Limitations:

The current version 1.1.0beta lacks the ability to set individual clearance values along differential pair and RF traces.

Also, there is currently no way to individually set clearances between conductive elements (traces, pours) and the copper fill generated by the plugin based on net voltages!

These settings become critical when voltages on outer layers exceed 30 volts and frequencies exceed a few megahertz.

Algorithm

Analyze the board outline, get geometry from the Edge.Cuts layer.
Collect all objects on the board: tracks, pads, vias, masks, and existing zones.
Divide the entire board into a certain number of sections (4-10). The number depends on your platform's capabilities.
Since the plugin is multi-threaded, each section is processed in parallel. Checks are performed for each element.
Automatic filling of the created zones.

The number of threads in the plugin is limited to 10. This number was chosen after testing the plugin with different thread counts.

Testing Methodology:

Processor: Intel Xeon Gold 5317 3.00GHz (12 cores / 24 threads) – 2 pcs (48 threads total)
Memory: 256GB DDR4 3.00GHz
Graphics Card: NVIDIA RTX A2000 6GB
Storage: SAS controller AVAGO MR9440-8i, 2 SAS HDD 1TB in RAID-1
Board: Test board size 76.55 x 71.05 mm
Fill Parameters: Circles 600 µm diameter, pitch 120 µm, fill density 90%
Measured Value: Total plugin execution time.

Tests Conducted:

The plugin was run with thread counts from 1 to 24. For each run, the following was recorded:

Preparation time (data reading).
Main loop time (shape generation and checking).
Final zone filling time.
Average time per shape.

Measurement results

Table 1. Summary of testing results

Threads	Main Loop, s	Preparation, s	Filling, s	Total Time, s	Speedup	Time/Shape, ms
1	121.02	1.20	5.93	128.15	1.00	11.42
2	68.47	1.18	5.92	75.57	1.70	5.83
3	45.56	1.18	5.92	52.66	2.43	3.88
4	38.14	1.20	5.92	45.26	2.83	2.91
5	30.55	1.19	5.92	37.66	3.40	2.34
6	28.23	1.17	5.87	35.27	3.63	1.98
7	23.81	1.32	5.71	30.84	4.15	1.69
8	21.91	1.20	6.02	29.13	4.40	1.49
9	25.52	1.19	5.92	32.63	3.93	1.34
10	22.90	1.17	5.82	29.89	4.29	1.23
11	23.12	1.16	5.92	30.20	4.24	1.11
12	25.54	1.31	5.92	32.77	3.91	1.06
13	16.16	1.18	6.02	23.36	5.48	1.03
14	23.21	1.17	5.92	30.30	4.23	0.98
15	15.27	1.17	6.02	22.46	5.70	0.98
16	25.46	1.18	6.02	32.66	3.92	0.96
17	17.99	1.17	5.92	25.08	5.11	0.96
18	29.43	1.15	5.92	36.50	3.51	0.91
19	26.18	1.17	6.03	33.38	3.84	0.91
20	19.86	1.17	6.02	27.05	4.74	0.92
21	14.78	1.16	5.92	21.86	5.86	0.93
22	31.66	1.19	5.82	38.67	3.31	0.87
23	28.65	1.19	5.94	35.78	3.58	0.84
24	25.51	1.14	5.72	32.37	3.96	0.86

It can be seen that speedup is nearly linear up to 8 threads. After 8 threads, the curve plateaus – adding more cores yields insignificant gains.

Amdahl's Law: Theory and Practice

The fraction of sequential code S was calculated using the formula:

Theoretical speedup according to Amdahl's Law:

.Table 2. Comparison with theory

Threads	Theory (S=0.0556)	Practice	Efficiency
1	1.00	1.00	100%
2	1.89	1.70	90%
4	3.51	2.83	81%
8	6.06	4.40	73%
12	7.78	3.91	50%
16	8.85	3.92	44%
24	9.88	3.96	40%

Figure 1 – Theoretical vs. Actual Speedup

Conclusions:

Optimal number of threads: 6-12. Further increase yields less than 10% speed gain while tripling resource consumption.
Parallelization efficiency: Up to 10 threads, efficiency is 73-90%, which is an excellent result for geometric computations.
Amdahl's Law in action: Even with an infinite number of cores, maximum speedup is limited to 18x due to the sequential portion. In practice, 5.86x was achieved.

Installation

Currently, the plugin is temporarily unavailable in the official KiCad repository, so installation is done from a file via the "Plugin and Content Manager":

Download the archive from the GitHub repository.

Open KiCad.
Go to Tools → Plugin and Content Manager.
Click the "Install from File" button. Select the downloaded archive.

The plugin has been tested on KiCad versions 8.0.5 to 8.0.7, as well as on 9.0.0, and works on Windows (10/11), Linux (Debian 13, Kubuntu 24).

Important Nuance: Technology vs. Electricals (Please Read Carefully!)

In the plugin settings, you will be asked to choose the board class (manufacturing accuracy, minimum clearances, etc.). This is where the main catch lies, and it's important to remember.

The board class (e.g., 3rd, 4th, 5th) determines the technological capabilities of the fab. It defines whether the manufacturer can make a 0.1mm clearance or needs a minimum of 0.2mm.
However, the board class does not guarantee the electrical safety of these clearances!

If your circuits are under high voltage (more than 30 volts), a 0.1mm clearance (technologically acceptable) may not satisfy electrical strength or leakage current requirements. Therefore, the plugin works on the following principle:

You specify the technological class (so it doesn't generate elements that the fab cannot etch).
You, as the designer, must pre-configure Net Classes in KiCad, assigning them proper clearances according to insulation classes (tables from GOST standards or manufacturer specifications).
The plugin respects these rules and will not intrude into areas where clearances are already defined by electrical rules and other constraints set in the PCB editor.

License (Important for Enthusiasts)

At the moment, the project is in a pre-release stage. The code can be freely copied and modified, but only for personal use.

Publishing forks or modified versions is currently prohibited.

But there's good news: as soon as the official release is out, the project will transition to the MIT open-source license. Then you'll be able to do whatever you want with it.

Conclusion

We hope Copper Filler proves useful for those who fine-tune boards before sending them to manufacturing. It automates routine tasks and helps make the board not only electrically more correct but also potentially cheaper to produce.

Use it, and may your boards be stable and your manufacturers happy!

Website link

Repository link

If you have ideas or find bugs, please write in Issues (but no PRs for now, as per the license).

Project Team: Alexander (aka @Sartorio), Mikhail (aka @mzakharov27), Tatyana (aka @MeowRr).

Copper Filler: Saving on PCB Manufacturing in KiCad