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Samsung expands GPU team: open RTL Designer and Performance Architect positions

The team at Samsung that designs the Xclipse GPU in Galaxy phones with Exynos SoC – is doing expansion. There are multiple jobs available, including positions in the RTL and Architecture teams:

• GPU RTL Design Engineer

• GPU Performance Architect (PPA)

These positions are in two locations:

• Samsung Advanced Computing Lab (ACL) in San Jose, California

• Samsung Austin Research and Development Center (SARC) in Austin,Texas

The compensations listed in the opening descriptions are base salaries only. The total compensation includes serious performance-based bonuses.

You can apply at the website – or, if you want, I can make you an internal referral since I (Yuri Panchul) am a member of the GPU team. Getting a referral from me is easy:

1. First, you solve the SystemVerilog Microarchitecture Challenge for AI No.2. Adding the Flow Control, an open-source challenge from Verilog Meetup – and send me the solution to yuri@panchul.com.

https://github.com/verilog-meetup/systemverilog-microarchitecture-challenge-for-ai-2

2. Then I discuss your solution with you either in person (if you live in the San Francisco Bay Area) or over Zoom. I don’t care whether you solve the challenge manually or use AI for it, but I need you to explain every single line of the solution. In addition to it, I may ask you a couple more questions (manual solutions only in front of me, no AI).

3. If I like your solutions, I will enter your data in the Samsung internal referral website. After that, you will get an email from the website and can start an application to go through the official Samsung interview process. I will also forward your resume to the hiring managers and the team’s recruiters.

4. Note that solving a couple of puzzles for me is not a part of the official Samsung interview process. This is just my personal way to ensure I forward only the relevant resumes to the company. Every single member of our RTL teams would solve such a thing easily, so this is not something difficult, just some basic techniques to design a static pipeline in Verilog, generic for the industry.

Our team consists of friendly, proficient, and helpful people. We also have a fancy office that just got 10-year anniversary:

Thank you,
Yuri Panchul