Gowin has clear advantages over Xilinx in the educational FPGA board market: Gowin boards are several times less expensive, the synthesis speed is several times faster, and the EDA package is two orders of magnitude smaller: we are talking about 1G versus 100G disk space. Of course, Xilinx is still the king of high-end prototyping boards that cost $10K-100K, but for the students such boards are irrelevant; such boards are for ASIC design companies. A beginning EE student needs a board for less than $100, and Gowin not only fits the bill but also covers all the needs, specifically:
Basic logic design labs: gates, muxes, arbiters, flops, FSMs.
Generating graphics, with LCD and DVI/HDMI output.
Sound recognition and sound generation.
Processing data from a camera.
Microarchitecture labs: data pipelines, FIFOs, memory controllers.
Simple CPUs / microcontroller-class cores with 3-5 pipeline stages.
A mid-range CPU with caches and TLBs that can run Linux (although for this one, you need Tang Mega 138K or at least Tang Primer 25K since Tang Nano 9K is too small for such an application).
In this post, we present a platform based on Sipeed Tang Nano 9K that reliably covers the needs for 1, 2, 3, 5 and 6. We are using Basic-Graphics-Music example set from the corresponding github repository).
We did not test our setup with a camera and we don’t think it is suitable to synthesize Linux-capable CPU cores, but it is more than enough for the first two years of digital electronic lab and computer architecture curriculum. And it costs less than $40 (compare it with Digilent Nexys A7 with Xilinx Artix-7 FPGA for $350 and Digilent Basys-3 for $165).
Gowin also wins a comparison against Altera, although not as clearly as against Xilinx:
There are inexpensive Altera-based boards from China, for example Saylinx for $54.
Altera Quartus synthesis is faster than Xilinx Vivado, although not to the degree of Gowin.
Altera EDA package is smaller, although not to the degree of Gowin.
Some may argue that Xilinx Spartan-6 boards are also inexpensive, but we cannot use them to teach the students. Spartan-6 is supported only by older EDA software Xilinx ISE, which does not support SystemVerilog, only Verilog-2001. We live in the 21st Century, and we want to teach the students SystemVerilog, that’s for sure.
Last but not least, Gowin users have the option to use both commercial and Yosys-based open toolchains. Yosys support for Xilinx does exist, but probably not as smooth as for Gowin (we did not evaluate Yosys for Xilinx firsthand).
There are more FPGA platforms, Lattice and Efinix; we are still in the process of evaluating them.
Now, let’s go back to Sipeed Tang Nano 9K. We plan to use it as one of the main platforms in Hacker Dojo in Mountain View, California, and for planned seminars in Central Asia. We already tried Gowin, Tang Primer 20K Dock board, as one of the boards on a seminar in Azerbaijan back in February 2024.
We presented our calculations in the following spreadsheet:
We will describe Tang Nano 20K and Tang Primer 25K Dock in separate posts. We should note that Tang Primer 25K Dock does not have LCD interface, so we have to buy an additional $35 HDMI screen for it to run all the labs.
Here is the list of all components of our Tang Nano 9K set:
TM1638 – a very convenient peripheral, especially for microarchitectural and CPU labs
I2S GY-PCM5102, for sound output.
Make sure you know how to put solder bridges, see the discussion here:
High-quality full-size breadboard
High-quality half-size breadboard, another option
Jumper 10cm Male-Male. If you prefer to put everything on a breadboard, you need to buy Male-Male jumpers; in other configurations you can use Male-Female and Female-Female jumpers.
Ear bud. It is without microphone, which is important. An ear bud with a microphone will not work with GY-PCM5102.
Rotary encoder. Useful for a practical exam.
Ultrasonic Sensor. Useful for a practical exam.
If you want to participate in porting labs and projects to the new boards, you can join Verilog meetups in Hacker Dojo in Mountain View, California, every Sunday from 11 am to 2 pm. If you are unable to come to Mountain View, you can join us online over Zoom at the same time. Please send an email to info@verilog-meetup.com, join Google Group meetsv and Telegram channel verilog_meetup to introduce yourself and get started.
If you are going to the Design Automation Conference (DAC) in San Francisco, California, I will be there on Monday, June 24, 2024. You can contact me on LinkedIn and we can discuss the board and education topics.
