Реверс-инжениринг КР580ВМ80А / i8080 завершен

Because we had a fairly general purpose instruction decoder programmed largely with PLA logic and some helper circuits, the instruction set could change easily. The initial ISA formatting and addressing modes were designed early, along with an initial set of required instructions. That was enough to generate a simulator, compiler and do initial programming for the chip – esp. including the OS. Once that was settled a bit, we (hardware engineers) had enough info to know:
— functional elements likely to be needed (like arbitrary bit-width extract/insert)
— where flexibility was needed (i.e. use µcode and PLAs)
Hardware development proceeded in parallel with OS, compiler and application programming. Useful new instructions for added OS capabilities, new OS data structures and the like:
--often appeared initially,
— quickly settled down to near nothing, and
— rarely changed the fundamental hardware design – it just required new PLA code.
Occasionally, we had to add some other structures in hardware – or signals between the chips – but it was rare enough to be “an interesting design problem” rather than “a disaster”. The set of instructions was well settled down about half-way through the design process, but the bit-encoding of them changed regularly – almost until the chip taped out (was committed to manufacturing masks).

the ISA could — and did — change several times a week depending on statistical analysis of code generated «to date», and
the compiler was updated in minutes to generate the new instruction set
The iAPX432 was a very good learning exercise for subsequent work with object-oriented languages
Very innovative structures were used on-chip: barrel shifters, bus-integrated ALU and address generation logic, folded PLAs, etc.
It was one of the 1st implementations of IEEE conformant 32-, 64- and 80-bit floating point
— we did LOTS of simulations of operations to minimize ULP (units-in-last-place) errors
It was the 1st chip at Intel that was fully register-transfer-level simulated, and mixed-level logic+RTL simulated
The IC layout design was fully connectivity extracted, and compared to the logic design for errors
— this procedure/process was hand validated by crawling around on a 30m x 30m chip plot tracing circuits
— we found the computer connectivity validation found many times more errors than the humans did