YuriPanchul Sep 15 2021 at 09:26High-level pipelining in TL-Verilog, RISC-V from Imagination, formal tools and open-source EDA on ChipEXPO in MoscowReading time3 minViews2.3KAlgorithms*Industrial Programming*FPGA*Programming microcontrollers*Manufacture and development of electronics*Total votes 3: ↑2 and ↓1+1Add to bookmarks2Comments2
NR_electronics Sep 28 2021 at 08:08Здравствуйте. Где можно посмотреть видео запись "19-я международная выставка электроники ChipEXPO-2021 " - ?
High-level pipelining in TL-Verilog, RISC-V from Imagination, formal tools and open-source EDA on ChipEXPO in Moscow