YuriPanchul Sep 15 2021 at 09:26 High-level pipelining in TL-Verilog, RISC-V from Imagination, formal tools and open-source EDA on ChipEXPO in Moscow Reading time 3 min Views 1.8K Algorithms *Industrial Programming *FPGA *Programming microcontrollers *Manufacture and development of electronics * Total votes 3: ↑2 and ↓1 +1 Add to bookmarks 2 Comments 2
NR_electronics Sep 28 2021 at 08:08 Здравствуйте. Где можно посмотреть видео запись "19-я международная выставка электроники ChipEXPO-2021 " - ?
High-level pipelining in TL-Verilog, RISC-V from Imagination, formal tools and open-source EDA on ChipEXPO in Moscow