Comments 3
VHDL failed to get traction at sign-off level because if couldn't do bi-directional components like pass-gates. Verilog (as VCS) was also a more efficient simulator. The IEEE VHDL committee refused to take any fixes for the bidirectional modeling, and now that SystemVerilog has UDNs it's in the same boat.
VHDL and Verilog could be easily interoperable, the whole SystemVerilog effort was somewhat redundant, but the EDA companies like to sell you more things rather than less. That can easily be done now with open-source tools (with FPGA acceleration).
Here are some fixes - https://docs.google.com/document/d/1PYPo_ZAiOtVXl53TDIBxyPwWoXFiwSpSYHCl3LPexXU/edit?usp=sharing
VHDL originated in depths of US military. It evolved from the ADA language and inherited some of its rigor. Rigor and familiarity were required.
Over time VHDL settled in inert areas: military, space, FPGA and Europe.
From an FPGA engineer's perspective, I see the following reasons why VHDL won't die anytime soon:
Design cycles of those inert areas sometimes span decades. E.g. some space stuff written 10-15 years ago have now been certified and ready for first launch.
FPGA EDA vendors don't swim in money. Therefore FPGA adoption of SystemVerilog modern features is lagging behind.
Existing code bases will not allow VHDL to evaporate, because they bring money.
Some interesting approaches and methodologies (especially from European industry and academia) are bringing new life to VHDL.
I admit, that ASIC design perspective is very different.
Sorry for thick russian accent.
Here is my take on Verilog-vs-VHDL In the early 1990s many people thought that Verilog was a temporary language and...