Authors
Ilia Mistiurin, Elena Tesmeeva.
Introduction
We developed different clock modes by using an FPGA board and Quartus Prime software. Available clock modes: clock, stopwatch, alarm, timer;
Hardware and software used
MAX 10 FPGA Device.
Buttons - input device.
LEDs and 7-Segment display - output device.
USB Blaster connector - to upload firmware.
Quartus Prime Lite Edition 18.1.
Verilog HDL.
Altera USB Blaster.
Technical implementation
Schematic representation
Program has four states, such as "Clock", "Alarm", "Stopwatch", "Timer". Default state is "Clock", then button click changes the state to following or modifies the current state.
For time count the module
decreased_clkwas implemented with standard MAX-10 CLK (50Hhz), that updates every 1000Hz.7-Segment Display
Display updates with the frequency ofdecreased_clkand shows the current time that changes according to state of the program.Each display has 8 cathodes (7 "sticks" and 1 "dot"), then every cathode powers up to show the digit.
Buttons
The problem is known as "Button bounce". Button click is an asynchronous event to our sequential FPGA logic, that updates onposedge clk, therefore the click might be detected few times or not detected at all.
The solution is to differentiate stable signals from false alarms using timer. You can read a detailed solution here.
Demonstration
(there should be a video)
Conclusion
We briefly described implement stages of different clock modes by using an FPGA board, Quartus Prime software and Verilog hardware description language. This work has been implemented in the scope of «Computer Architecture» course in the Innopolis University. This implementation can be extended for use in the educational process.
Acknowledgement
The authors would like to express gratitude to our professors Artem Burmyakov, Alexander Tormasov and to our teacher assistant Mike Kuskov for giving us deep knowledge and possibility to use them in practice.
References