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The results of 7 Verilog meetups + the goals and the steps going forward

Reading time 5 min
Views 582

Since the New Year we had 7 Verilog meetups at HackerDojo. We discussed the modern way of designing digital circuits using hardware description languages, the exercises on FPGA boards and the topic of microarchitecture. For the last two sessions we went over the most basic CPU core that can be used as a baseline for further exercises.

Now, in order to make progress toward the goal of creating new educational materials, it is essential for the regular participants to solve all the homework exercises (see the details in the post below) in parallel with studying the recommended materials.

The next steps are:

1) We are going to do weekly Zoom calls on Sundays, starting March 24, 2024 at 11 am California time (summer time). The link. During this call we are going to discuss the SystemVerilog Homework and the individual projects.

2) Once we develop more materials, we are going to organize a Show-and-Tell session in Hacker Dojo, for a wider audience. During the session several participants from the core team will present demos on various FPGA boards and explain to the curious how FPGA and ASIC work.

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Total votes 5: ↑4 and ↓1 +3
Comments 0

Bootstrapping Azerbaijan as a new center of ASIC design + Verilog Meetup #6 in Silicon Valley

Reading time 11 min
Views 1.5K

Last week I was doing a seminar on SystemVerilog, ASIC and FPGA at ADA University in Baku, Azerbaijan. I will replicate the last two sessions of this seminar, on RISC-V CPU simulation and synthesis, at the Verilog Meetups on March 3 and March 10 at Hacker Dojo, Mountain View, California. For this reason I am combining the information about Azerbaijan and California seminars in a single post.

First, let's talk about ADA University.

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Total votes 8: ↑7 and ↓1 +6
Comments 0

Verilog Meetups @ Hacker Dojo: the status and the plans for February 2024

Reading time 9 min
Views 1.8K

The first three meetups of the Portable SystemVerilog Examples group at Hacker Dojo in Mountain View, California were a kind of brainstorming sessions. We discussed the electronic industry, the essence of modern chip design, and the challenges to educate new design engineers. Now we are moving into a new mode of action. We are going to have weekly meetings of the core R&D team and monthly or bi-monthly events for a larger audience.

We are focusing on interview-level microarchitectural and CPU design examples, providing FPGA vendor-neutral infrastructure and compatibility with open-source ASIC design tools.

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Total votes 3: ↑3 and ↓0 +3
Comments 3

Portable SystemVerilog Examples for ASIC and FPGA: the results of the meetup on 2024-01-21 and the next steps

Reading time 4 min
Views 1.2K

The second meetup of the Portable SystemVerilog Examples group on January 21 2024 at Hacker Dojo in Mountain View, California, went as planned: we moved from the stage of presenting the project to the self-introductions of the participants and the initial tutorial with the first examples. We also started distributing the tasks. The next meetup is tentatively scheduled for January 28 at the same location, from 2 pm to 5 pm. The contents of the meeting will be to work on the examples: basics-graphics-music and systemverilog-homework.

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Total votes 2: ↑1 and ↓1 0
Comments 0

The next steps after a good meetup on Portable SystemVerilog Examples for ASIC and FPGA

Reading time 4 min
Views 708

The meetup on January 14 at Hacker Dojo in Mountain View, California, went well, although not as planned - we spent almost all the time talking instead of doing hands-on exercises. The room we booked can fit 30 people and approximately 30 people did show up. The quality of participants was high: approximately half were familiar with hardware description languages and another half came from various software topics. 12 people filled out the questionnaire despite the fact that I forgot to bring 30 pens.

The discussion during and after the presentation was focused and very meaningful: microarchitecture and education, EDA infrastructure / build scripts, open-source ASIC design tools, the economics of ASIC design and manufacturing, high-level synthesis, transaction-level modeling, ASIC prototyping using FPGA boards, FPGA embedded in ASIC (Menta), new FPGA manufacturers (Gowin) and new design languages - Chisel and SpinalHDL.

Four persons came to me after the meeting to discuss their participation in working on open-source portable SystemVerilog examples, and another seven expressed this intention in the questionnaire. So we are meeting again in Hacker Dojo on Sunday, January 21, at 2 PM, this time not in the classroom area, but in the common shared area.

Generally, I am thinking of having regular meetings, probably on a weekly basis for a small team of developers of the educational materials and on a monthly basis for a wider audience, discussing various design and verification topics.

There were two correspondents of Slavic Sacramento who recorded the video of the presentation. They are going to make it available soon.

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Total votes 7: ↑6 and ↓1 +5
Comments 2

Why would a software engineer attend an FPGA hardware meetup at Hacker Dojo?

Reading time 6 min
Views 1.1K

For the last 30 years digital chip design is not a schematic entry anymore: hardware engineers write code just like software engineers.

The difference is that the code software engineer writes becomes a chain of CPU instructions stored in memory, while the code in a hardware description language (HDL) becomes the CPU itself, its transistors and metal connections. And not only a CPU: the same technique is used to design processor-less ("fixed function") blocks in GPU that shuffle triangles and pixels, as well as network router chips that edit packet headers 100 times faster than CPU.

There are ways to experience this workflow without paying a million dollars to a silicon fab. One way is simulation, and another way is to use a matrix of reconfigurable logic cells, a Field Programmable Gate Array (FPGA). You can come on January 14 to Hacker Dojo in Mountain View, California. We have a bunch of computers and FPGA boards, and we will show you how to use them not only to blink LEDs but also to output graphics and recognize music.

This will change your perspective of what the code is.

Prepare for a ride:
Total votes 8: ↑6 and ↓2 +4
Comments 0

Toward the January meetup on portable SystemVerilog examples in Silicon Valley

Reading time 4 min
Views 1.1K

The team developing a set of portable SystemVerilog examples decided to organize the first event in Silicon Valley on Sunday, January 14 from 2PM till 5PM at Hacker Dojo in Mountain View, CA. If the first event is successful we are going to make it recurrent. You can register for the event on Meetup or LinkedIn.

The current directions of the group:

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Total votes 10: ↑8 and ↓2 +6
Comments 0

The first Silicon Valley meetup on portable SystemVerilog examples for ASIC and FPGA

Reading time 3 min
Views 922

Need to start your career or hobby in digital design and verification of silicon chips or reconfigurable hardware? Explore multiple FPGA toolchains and open-source ASIC tools? Design your own RISC-V CPU or ML accelerator? Prepare for an interview in SystemVerilog? Come to our first Silicon Valley meetup on portable SystemVerilog examples for ASIC and FPGA.

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Total votes 4: ↑3 and ↓1 +2
Comments 2

Exploring VALID/READY protocol, pipelines and experimenting with flow control using an HDL training tool

Level of difficulty Medium
Reading time 1 min
Views 1K

Ссылка на русскую версию / link to Russian version

Understanding valid/ready protocol is extremely important for every microarchitect.

Valid/ready is one of the main protocols used to organise flow-control inside a logic block as well as on inter-block (SoC) level.

In the last lesson, we explored FIFO buffer using hdlgadgets - human-in-the-loop HDL training tool.

This time we will take two FIFO buffers (which form a pipeline with valid/ready handshakes) and will experiment with it by changing flow-control logic of the pipeline.

We will show that valid/ready is not only a mechanism for transferring data from one FIFO queue to another, but also a method for organizing various kinds of logical functionality between queues.

If you have not worked with valid/ready protocol before, you will be surprised how easy it is to achieve desired functionality of the design by simply writing couple of lines of Verilog code in the handshaking logic block between two FIFOs.

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Total votes 6: ↑6 and ↓0 +6
Comments 0

Exploring FIFO principles using an HDL training tool

Level of difficulty Medium
Reading time 1 min
Views 597

Ссылка на русскую версию / link to Russian version

FIFO is a key concept in hardware design. Understanding of FIFO is necessary for understanding the valid/ready protocol, which in turn is necessary for organisation of flow-control within a design.

Unfortunately, there are very few books on this topic, and to be fair, microarchitectural concepts are quite difficult to master from books, since understanding of these concepts are coming with practice. In other words it is more about developing hardware intuition.

The idea of the HDL training tool is that it can help develop a hardware intuition, providing the opportunity to explore ready-made scenarios in a step-by-step interactive way. The tool also provides detailed visualization of a simulated scenario.

Since the tool is a front-end for the HDL simulator, the real, synthesized SystemVerilog is executed on the simulator itself, which can be viewed and even modified.

So, the video of exploring FIFO on the training tool is here:

Watch the video and continue reading
Total votes 4: ↑4 and ↓0 +4
Comments 0

http://GuitarFX.Net Digital (SOFTWARE) modeling of analog guitar distortion, reverb, noise gate etc. effects

Reading time 5 min
Views 1.3K

The sound of rock music, in particular of hard rock and heavy metal, is largely based on a specially distorted guitar sound, for which electronic “distortion” devices, tube amplifiers in “overloaded” mode, computers with appropriate software and digital processors are used. increasingly using neural network algorithms.

The distorted sound of electric guitars began to gain popularity around the 1960s. Since that time, the sound of overloaded tube amplifiers, connected to powerful dedicated guitar speakers with large dedicated speakers, has been considered the benchmark in rock music. But tube amplifiers were relatively expensive and inconvenient to operate. Therefore, semiconductor distortion devices were developed.

At that time, the electrical circuitry of distortion devices was relatively simple and the signal output from their output only vaguely resembled the sound of an overloaded tube amplifier. Nevertheless, it was still somewhat similar to the “sound of a lamp” and this provided a powerful incentive for designers of analog semiconductor distortion circuits to continue their research, complicate circuits and propose new circuit solutions. The heyday of analog solid-state distortion was around 1995-2010. The most popular were electrical circuit diagrams like those shown in the figure below.

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Total votes 3: ↑3 and ↓0 +3
Comments 4

Android for electronics design engineers

Reading time 5 min
Views 1.8K

There is a list of well-known electronics design tools for Android which can be found in every review for the last 10 years: “Electrodoc”, “Every Circuit”, “Droid Tesla”, “Electronics Toolbox”, “RF & Microwave Toolbox” and so on. Also, there is a lot of trash on the market that turns finding a good tool into a quest.

This short review is about an unknown but cool tool “Circuit Calculator” working on Android devices and intended for professional electronics designers.

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Total votes 4: ↑4 and ↓0 +4
Comments 0

“FPGA InsideOut” – animation about CRC and parallel CRC calculation

Reading time 2 min
Views 1.4K

Ссылка на русскую версию / link to Russian version

FPGA InsideOut is an attempt to make a set of educational FPGA videos presented in the “human-in-the-loop” style. In these videos we will not only show how we are interfacing with an actual FPGA board but will also provide synchronous real-time visualisation of FPGA's internal logic.

For our first video we have picked a CRC circuit (cycle redundancy check) which is based on a linear feedback shift register. This circuit goes through several transformations during the course of the video. Intrigued? - let’s watch the video.

Watch the video and continue reading
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Making an Encoder Cable for Servosila Brushless Motor Controller. Testing in Direct Drive mode

Reading time 2 min
Views 866

In this video, we are making a cable for connecting a quadrature encoder to a Servosila brushless motor controller, and and then running a servo motor in Direct Drive mode. To make the cable we are using a cable assembly kit that can be purchased from the internet store. Alternatively, the components for the cable can be bought in other places. The part numbers are given in the controller's datasheet.

The cable assembly kit consists of a connector and a set of wires with pre-crimped socket blades. If you have a crimper tool, you can also attach the socket blades to wires by yourself.

Lets open a datasheet document that comes with the brushless motor controller. Note that each connector has its first pin clearly marked with a "1" sign. Conventionally, the numbering of pins is done in such a way that there are rows of odd-numbered and even-numbered pins.

The quadrature encoder's electrical interface has 5 wires in total. Positions of the pins of each of the wires are given in the table. The socket blades need to be pushed into the connector until you feel a "click". The blades lock into the connector's sockets. Optionally, primarily for cosmetic reasons, you may want to add a heat-shrink tubing to your cable.

The brushless motor controllers come in two distinct forms, a circular and a rectangular one. Both models are identical in terms of capabilities, features, firmware, and external electrical connectors.

The connector has a locking mechanism that keeps it in place. I soldered a mating connector to the other side of the cable - a connector that my brushless motor needs. Note that your motor will likely require a different connector, or no connector at all. It is always a good idea to test an end-to-end integrity of the cable and its connectors. Lets buzz the wires using a multimeter. The cable is ready.

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Total votes 5: ↑3 and ↓2 +1
Comments 0

SEPIC-Ćuk split-rail converter average model

Reading time 4 min
Views 1.4K

SEPIC-Ćuk split-rail converter can be used to make positive and negative supplies from a single input voltage for relatively well-matched loads like operational amplifiers.

Transient models are time consuming. Average models reduce modeling time drastically.

The PWM switch average models for current- and voltage-mode are described in details in Christophe Basso’s book “Switch-Mode Power Supplies, Second Edition: SPICE Simulations and Practical Designs”. Using of these models for SEPIC and Ćuk converters is also shown.

This text shows how to use the PWM switch average model to design a split-rail SEPIC-Ćuk converter.

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Total votes 4: ↑4 and ↓0 +4
Comments 0

High-level pipelining in TL-Verilog, RISC-V from Imagination, formal tools and open-source EDA on ChipEXPO in Moscow

Reading time 3 min
Views 2.1K

This year ChipEXPO conference in Moscow invited several Western speakers to present in English the emerging technologies in high-level HDLs, formal verification, open-source EDA and using industrual RISC-V cores for education. You can join these presentations on September 14-16 for free using this link (you may need to use google translate from Russian to go through the registration) https://eventswallet.com/en/events/282/

The whole program is here

The English-speaking presentations and tutorials include:

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Total votes 3: ↑2 and ↓1 +1
Comments 2

UAVCAN HITL UAV Simulator for PX4

Reading time 2 min
Views 2.5K

Hi from RaccoonLab, a team of enthusiasts in field robotics! We want to share our true-HITL UAVCAN-based simulator for PX4.

We believe a unified UAVCAN bus for drone onboard electronics will become a mainstream approach shortly. Our simulator is already based on UAVCAN (in opposition to UART-MAVLINK) and emulates exactly the same messages as real UAVCAN-sensors.

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Total votes 2: ↑2 and ↓0 +2
Comments 0

A note on small-signal modeling of SEPIC CM CCM

Reading time 6 min
Views 3.1K

Knowing parameters of small-signal control-to-output transfer functions makes it easier for engineers to design compensation networks of DC/DC converters. The equations for SEPIC can be found in different works and Application Notes, but there are differences. A work has been done to solve this problem.

Simplified design equations for SEPIC with Current Mode control (CM) in Continuous Conduction Mode (CCM) suitable for practical design of compensation networks are shown.

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Total votes 3: ↑3 and ↓0 +3
Comments 0
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