Написал лонгрид на английском о текущем состоянии открытых средств проектирования ASIC-ов. Заодно познакомил англоязычных читателей с практиками шаманов Сибири и фигурой Ивана Сусанина. Упомянул планируемые семинары в Мексике и Армении.
A text on the current state of Open-source ASIC design tools. Includes side discussions of the upcoming hackathons in Mexico and Armenia, Docker and Python, Static Timing Analysis and RISC-V, Siberian shamans and treacherous swamps in Belarus.
Since the New Year we had 7 Verilog meetups at HackerDojo. We discussed the modern way of designing digital circuits using hardware description languages, the exercises on FPGA boards and the topic of microarchitecture. For the last two sessions we went over the most basic CPU core that can be used as a baseline for further exercises.
Now, in order to make progress toward the goal of creating new educational materials, it is essential for the regular participants to solve all the homework exercises (see the details in the post below) in parallel with studying the recommended materials.
The next steps are:
1) We are going to do weekly Zoom calls on Sundays, starting March 24, 2024 at 11 am California time (summer time). The link. During this call we are going to discuss the SystemVerilog Homework and the individual projects.
2) Once we develop more materials, we are going to organize a Show-and-Tell session in Hacker Dojo, for a wider audience. During the session several participants from the core team will present demos on various FPGA boards and explain to the curious how FPGA and ASIC work.
The first meetups of the Portable SystemVerilog Examples group at Hacker Dojo in Mountain View, California were a kind of brainstorming sessions. We discussed the electronic industry, the essence of modern chip design, and the challenges of educating new design engineers. Then we moved to a new mode of action. We started weekly meetings of the core R&D team with the goal to prepare educational materials for the events for a larger audience. The meetings are generally held on Sundays from 11 pm to 2 pm. If you cannot come to Mountain View, you can join online.
We are focusing on interview-level microarchitectural and CPU design examples, providing FPGA vendor-neutral infrastructure and compatibility with open-source ASIC design tools.
In order not to buy a defective monitor, it is highly recommended to check it before buying. DE10-Lite is great for this because of a compact size and the presence of a VGA connector.
Demid Efremov and Ivan Kornienko.
Music box on Verilog HDL for Cyclone IV.
Need to start your career or hobby in digital design and verification of silicon chips or reconfigurable hardware? Explore multiple FPGA toolchains and open-source ASIC tools? Design your own RISC-V CPU or ML accelerator? Prepare for an interview in SystemVerilog? Come to our first Silicon Valley meetup on portable SystemVerilog examples for ASIC and FPGA.
Games can give positive emotions and provide relaxation to a person. However, the main purpose of my project is to get a better understanding of the Verilog language. In addition, coding a game into FPGA will help to define the bounds of this programming language.
This year ChipEXPO conference in Moscow invited several Western speakers to present in English the emerging technologies in high-level HDLs, formal verification, open-source EDA and using industrual RISC-V cores for education. You can join these presentations on September 14-16 for free using this link (you may need to use google translate from Russian to go through the registration) https://eventswallet.com/en/events/282/
The whole program is here
The English-speaking presentations and tutorials include:
There are many situations when you need to protect your data, and different tools can be used to do that. For example, a safe. We develop a passcode data protection mechanism by using an FPGA board and Quartus Prime software. It allows demonstrating the basic concepts of a combination lock such as entering data, setting and checking a passcode, and displaying data.
