Pull to refresh

“FPGA InsideOut” – animation about CRC and parallel CRC calculation

Reading time2 min

Ссылка на русскую версию / link to Russian version

FPGA InsideOut is an attempt to make a set of educational FPGA videos presented in the “human-in-the-loop” style. In these videos we will not only show how we are interfacing with an actual FPGA board but will also provide synchronous real-time visualisation of FPGA's internal logic.

For our first video we have picked a CRC circuit (cycle redundancy check) which is based on a linear feedback shift register. This circuit goes through several transformations during the course of the video. Intrigued? - let’s watch the video.

As we just saw it is easy to start with a simple concept and “unfold a story” from it. In our video we  explained not just a shift register circuit but also some theory behind CRC calculation and a method of converting a shift register into a parallel CRC circuit. Along the way we also demonstrated some signal propagation patterns through the combinational and sequential logic of the circuit.

Here are some interesting candidates for experiments that are going to be covered in the future sessions: stream interfaces, pipelines, FIFOs, timings (STA), etc.

Long time before FPGAs came about Confucius said – “I see and I remember, I do and I understand”. It is hard to disagree with this principle and this is why we also try to accompany our videos with Verilog code. This way you can replicate those designs yourself and explore them deeper on your own FPGA board.

In the next article I will explain how such videos can be produced. I will also introduce a set of Python scripts for making them. The software will soon be published on Github - maybe it will be useful to someone who wishes to create similar videos, or maybe, community members would want to improve or contribute to its development.

On this, I want to say thank you for your attention - your comments are very welcome.