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Programmable logic integrated circuits

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Exploring FIFO principles using an HDL training tool

Level of difficulty Medium
Reading time 1 min
Views 339

Ссылка на русскую версию / link to Russian version

FIFO is a key concept in hardware design. Understanding of FIFO is necessary for understanding the valid/ready protocol, which in turn is necessary for organisation of flow-control within a design.

Unfortunately, there are very few books on this topic, and to be fair, microarchitectural concepts are quite difficult to master from books, since understanding of these concepts are coming with practice. In other words it is more about developing hardware intuition.

The idea of the HDL training tool is that it can help develop a hardware intuition, providing the opportunity to explore ready-made scenarios in a step-by-step interactive way. The tool also provides detailed visualization of a simulated scenario.

Since the tool is a front-end for the HDL simulator, the real, synthesized SystemVerilog is executed on the simulator itself, which can be viewed and even modified.

So, the video of exploring FIFO on the training tool is here:

Watch the video and continue reading
Total votes 4: ↑4 and ↓0 +4
Comments 0


Reading time 2 min
Views 1.1K

We are the first year students studying Computer Science in Innopolis University and we would like to share our experience in developing a Verilog program to create the greatest Memory Game (MemGame) that has ever existed on the FPGA board.

In this article, we decided to create a game for extending human memory. You will read the background theory and the incredible story of creation.

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Total votes 6: ↑6 and ↓0 +6
Comments 1

“FPGA InsideOut” – animation about CRC and parallel CRC calculation

Reading time 2 min
Views 1.3K

Ссылка на русскую версию / link to Russian version

FPGA InsideOut is an attempt to make a set of educational FPGA videos presented in the “human-in-the-loop” style. In these videos we will not only show how we are interfacing with an actual FPGA board but will also provide synchronous real-time visualisation of FPGA's internal logic.

For our first video we have picked a CRC circuit (cycle redundancy check) which is based on a linear feedback shift register. This circuit goes through several transformations during the course of the video. Intrigued? - let’s watch the video.

Watch the video and continue reading
Rating 0
Comments 0

The Dino game from Google Chrome using FPGA

Reading time 4 min
Views 3.1K

Many people are familiar with the situation when there is no Internet, and a small dinosaur appears on the Google Chrome screen. Today we will tell you how to implement this game on the Cyclone IV FPGA board.

We are Yegor Blinov, Egor Kuziakov, and Inga Ezhova - the first-year students of Innopolis University. In our program, there was a course "Computer Architecture", where we had labs with FPGA boards Cyclone IV and MAX10. We were inspired by this equipment and decided to implement the project on one of the boards.

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Total votes 7: ↑7 and ↓0 +7
Comments 3

High-level pipelining in TL-Verilog, RISC-V from Imagination, formal tools and open-source EDA on ChipEXPO in Moscow

Reading time 3 min
Views 1.9K

This year ChipEXPO conference in Moscow invited several Western speakers to present in English the emerging technologies in high-level HDLs, formal verification, open-source EDA and using industrual RISC-V cores for education. You can join these presentations on September 14-16 for free using this link (you may need to use google translate from Russian to go through the registration) https://eventswallet.com/en/events/282/

The whole program is here

The English-speaking presentations and tutorials include:

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Total votes 3: ↑2 and ↓1 +1
Comments 2

System-on-Chip bus: AXI4 simplified and explained

Reading time 20 min
Views 19K

Protocol AXI4 was developed for High-bandwidth and low latency applications. It is designed to allow communication between master and slave devices. Master is typically a DMA or CPU and slaves are DRAM controllers, or other specific protocol controllers: UART, SPI, and others. Sometimes one component can implement multiple instances of this protocol. Usually, a prefix is used to differentiate between multiple AXI4 interfaces.

For example, Ethernet MAC can integrate DMA and slave interface used to command MAC. MAC can accept commands on the slave interface that contain data about the location of the next ethernet packet and MAC can start fetching this packet using the separate master interface instance.

This article was motivated by common design mistakes AXI4 designers make when they are designing their Digital IP. (Looking at you Xilinx)

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Total votes 10: ↑10 and ↓0 +10
Comments 1

Koyaanisqatsi: The WYSIWYG-style byte-code CPU

Reading time 5 min
Views 1.3K
Draft diagram of core

SVG-File (actual draft)


Ancient times are known to everyone not with immortal works from Homer's only, but also with the Pythagorean multiplication table, Euclidean geometry and the Archimedes screw and the Pi, which we learned to use only relatively recently. In antiquity the art was not only to be able to write poetry and prose, but to design catapults or battering tools also, now there are rigid frameworks, when the discovering the new another beautiful formula is a formal words play only.
Mathematics rules the modern world completely, cynically intertwining with the world of art, intruding with calculations in all spheres of our recreation and everyday life, when the colors of masterpieces turning into poisonous colours.
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Total votes 2: ↑2 and ↓0 +2
Comments 0

Passcode Data Protection by Using FPGA and Verilog

Reading time 4 min
Views 2.5K

There are many situations when you need to protect your data, and different tools can be used to do that. For example, a safe. We develop a passcode data protection mechanism by using an FPGA board and Quartus Prime software. It allows demonstrating the basic concepts of a combination lock such as entering data, setting and checking a passcode, and displaying data.

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Total votes 5: ↑3 and ↓2 +1
Comments 0

Building a Bare-Metal Application on Intel Cyclone V for Absolute Beginners

Reading time 7 min
Views 8.1K
Setting up Linux on the development board like SocKit with a double-core ARM Cortex A9 is not rocket science. A manufacturer of the board supports the ready-to-use image, appropriate for installing on SD card or another media. But what if you are craving to touch bare metal, approaching a neck-breaking speed of code not restrained by an OS core? Well, it is possible, but not so easy and obvious. In this short essay, I'll give you step-by-step instruction, how to build and run you first bare-metal application on Cyclone V SoC, that uses ARM Cortex A9 core of the HPS subsystem of the SoC.

You need to have the development board with Intel (Altera) Cyclone V SoC. I used SoCKit board:

Ready? Let's go!
Total votes 13: ↑11 and ↓2 +9
Comments 2

Physical unclonable functions: protection for electronics against illegal copying

Reading time 7 min
Views 4.9K

Source: The online counterfeit economy: consumer electronics, a report made by CSC in 2017

Over the past 10 years, the number of fake goods in the world has doubled. This data has been published in the latest Year-End Intellectual Property Rights Review by the US Department of Homeland Security in 2016 (the most current year tracked). A lot of the counterfeiting comes from China (56%), Hong Kong (36%) and Singapore (2%). The manufacturers of original goods suffer serious losses, some of which occur on the electronics market.

Many modern products contain electronic components: clothes, shoes, watches, jewellery, cars.
Last year, direct losses from the illegal copying of consumer electronics and electronic components in the composition of other goods were about $0.5 trillion.

How to solve this problem?
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Total votes 14: ↑14 and ↓0 +14
Comments 0

System in Package, or What's Under Chip Package Cover?

Reading time 7 min
Views 4.7K
Transistor feature size is decreasing despite constant rumors about the death of Moore’s law and the fact that industry is really close to physical limits of miniaturisation (or even went through them with some clever technology tricks). Moore’s law, however, created user’s appetite for innovation, which is hard to handle for the industry. That’s why modern microelectronic products aren’t just feature size scaled, but also employ a number of other features, often even more complicated than chip scaling.

Disclaimer: This article is a slightly updated translation of my own piece published on this very site here. If you're Russian-speaking, you may want to check the original. If you're English-speaking, it's worth noting that English is not my native language, so I'll be very grateful for the feedback if you find something weird in the text.
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Total votes 38: ↑38 and ↓0 +38
Comments 0

A Practical Implementation of the Switching Generator Using Verilog HDL

Reading time 10 min
Views 2.8K


Linear feedback shift registers are an excellent tool for implementing a pseudo random bit generator in hardware; they inhibit a simple and efficient electronic structure. Further, they are capable of producing output sequences with large periods and good statistical properties. However, standard LFSRs are not cryptographically secure, since the output sequence can be uniquely predicted given a small number of key stream bits using Berlekamp-Massey algorithm. Several methods have been proposed to destroy the linearity inherent in LFSR design. These methods include nonlinear combination generators, nonlinear filter generators, and clock controlled generators. Nevertheless, they remain vulnerable to many attacks such as side channel attacks and algebraic attacks. In 2015, a new clocked controlled generator, called the switching generator, was proposed. This new generator has been proven to be resistant to algebraic attacks and side channel attacks, while preserving efficiency and security requirements. In this project, we present a design of the switching generator using Verilog HDL.
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Total votes 16: ↑12 and ↓4 +8
Comments 9

Real-time edge detection using FPGA

Reading time 8 min
Views 14K


Our project implements a real-time edge detection system based on capturing image frames from an OV7670 camera and streaming them to a VGA monitor after applying a grayscale filter and Sobel operator. Our design is built on a Cyclone IV FPGA board which enables us to optimize the performance using the powerful features of the low-level hardware and parallel computations which is important to meet the requirements of the real-time system.

We used ZEOWAA FPGA development board which is based on Cyclone IV (EP4CE6E22C8N). Also, we used Quartus Prime Lite Edition as a development environment and Verilog HDL as a programming language. In addition, we used the built-in VGA interface to drive the VGA monitor, and GPIO (General Pins for Input and Output) to connect the external hardware with our board.

ZEOWAA FPGA development board

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Total votes 55: ↑41 and ↓14 +27
Comments 46

Stack-based calculator on the Cyclone IV FPGA board

Reading time 12 min
Views 9.5K


As first-year students of Innopolis University, we had an opportunity to make our own project in computer architecture. University suggested us several projects and we have chosen to make a stack-based calculator with reverse polish notation. One of the requirements for the project is to use FPGA board provided by the university.

As our board, we have chosen Cyclon IV. Therefore, we had to write code on hardware description language. In the course we have studied Verilog, so we have chosen it. Also, the university has additional modules for FPGA, such as numpad, thus we decided to use it in our project.

In this article, we want to share our knowledge about FPGA and Verilog, also provide you with a tutorial to repeat our project.
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Total votes 75: ↑58 and ↓17 +41
Comments 27

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