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Bootstrapping Azerbaijan as a new center of ASIC design + Verilog Meetup #6 in Silicon Valley

Reading time 11 min
Views 935

Last week I was doing a seminar on SystemVerilog, ASIC and FPGA at ADA University in Baku, Azerbaijan. I will replicate the last two sessions of this seminar, on RISC-V CPU simulation and synthesis, at the Verilog Meetups on March 3 and March 10 at Hacker Dojo, Mountain View, California. For this reason I am combining the information about Azerbaijan and California seminars in a single post.

First, let's talk about ADA University.

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Total votes 6: ↑6 and ↓0 +6
Comments 0

Verilog Meetups @ Hacker Dojo: the status and the plans for February 2024

Reading time 9 min
Views 1.3K

The first three meetups of the Portable SystemVerilog Examples group at Hacker Dojo in Mountain View, California were a kind of brainstorming sessions. We discussed the electronic industry, the essence of modern chip design, and the challenges to educate new design engineers. Now we are moving into a new mode of action. We are going to have weekly meetings of the core R&D team and monthly or bi-monthly events for a larger audience.

We are focusing on interview-level microarchitectural and CPU design examples, providing FPGA vendor-neutral infrastructure and compatibility with open-source ASIC design tools.

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Total votes 3: ↑3 and ↓0 +3
Comments 3

Portable SystemVerilog Examples for ASIC and FPGA: the results of the meetup on 2024-01-21 and the next steps

Reading time 4 min
Views 1.1K

The second meetup of the Portable SystemVerilog Examples group on January 21 2024 at Hacker Dojo in Mountain View, California, went as planned: we moved from the stage of presenting the project to the self-introductions of the participants and the initial tutorial with the first examples. We also started distributing the tasks. The next meetup is tentatively scheduled for January 28 at the same location, from 2 pm to 5 pm. The contents of the meeting will be to work on the examples: basics-graphics-music and systemverilog-homework.

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Total votes 2: ↑1 and ↓1 0
Comments 0

The next steps after a good meetup on Portable SystemVerilog Examples for ASIC and FPGA

Reading time 4 min
Views 664

The meetup on January 14 at Hacker Dojo in Mountain View, California, went well, although not as planned - we spent almost all the time talking instead of doing hands-on exercises. The room we booked can fit 30 people and approximately 30 people did show up. The quality of participants was high: approximately half were familiar with hardware description languages and another half came from various software topics. 12 people filled out the questionnaire despite the fact that I forgot to bring 30 pens.

The discussion during and after the presentation was focused and very meaningful: microarchitecture and education, EDA infrastructure / build scripts, open-source ASIC design tools, the economics of ASIC design and manufacturing, high-level synthesis, transaction-level modeling, ASIC prototyping using FPGA boards, FPGA embedded in ASIC (Menta), new FPGA manufacturers (Gowin) and new design languages - Chisel and SpinalHDL.

Four persons came to me after the meeting to discuss their participation in working on open-source portable SystemVerilog examples, and another seven expressed this intention in the questionnaire. So we are meeting again in Hacker Dojo on Sunday, January 21, at 2 PM, this time not in the classroom area, but in the common shared area.

Generally, I am thinking of having regular meetings, probably on a weekly basis for a small team of developers of the educational materials and on a monthly basis for a wider audience, discussing various design and verification topics.

There were two correspondents of Slavic Sacramento who recorded the video of the presentation. They are going to make it available soon.

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Total votes 7: ↑6 and ↓1 +5
Comments 2

Why would a software engineer attend an FPGA hardware meetup at Hacker Dojo?

Reading time 6 min
Views 1.1K

For the last 30 years digital chip design is not a schematic entry anymore: hardware engineers write code just like software engineers.

The difference is that the code software engineer writes becomes a chain of CPU instructions stored in memory, while the code in a hardware description language (HDL) becomes the CPU itself, its transistors and metal connections. And not only a CPU: the same technique is used to design processor-less ("fixed function") blocks in GPU that shuffle triangles and pixels, as well as network router chips that edit packet headers 100 times faster than CPU.

There are ways to experience this workflow without paying a million dollars to a silicon fab. One way is simulation, and another way is to use a matrix of reconfigurable logic cells, a Field Programmable Gate Array (FPGA). You can come on January 14 to Hacker Dojo in Mountain View, California. We have a bunch of computers and FPGA boards, and we will show you how to use them not only to blink LEDs but also to output graphics and recognize music.

This will change your perspective of what the code is.

Prepare for a ride:
Total votes 8: ↑6 and ↓2 +4
Comments 0

Toward the January meetup on portable SystemVerilog examples in Silicon Valley

Reading time 4 min
Views 1K

The team developing a set of portable SystemVerilog examples decided to organize the first event in Silicon Valley on Sunday, January 14 from 2PM till 5PM at Hacker Dojo in Mountain View, CA. If the first event is successful we are going to make it recurrent. You can register for the event on Meetup or LinkedIn.

The current directions of the group:

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Total votes 10: ↑8 and ↓2 +6
Comments 0

The first Silicon Valley meetup on portable SystemVerilog examples for ASIC and FPGA

Reading time 3 min
Views 895

Need to start your career or hobby in digital design and verification of silicon chips or reconfigurable hardware? Explore multiple FPGA toolchains and open-source ASIC tools? Design your own RISC-V CPU or ML accelerator? Prepare for an interview in SystemVerilog? Come to our first Silicon Valley meetup on portable SystemVerilog examples for ASIC and FPGA.

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Total votes 4: ↑3 and ↓1 +2
Comments 2

Exploring VALID/READY protocol, pipelines and experimenting with flow control using an HDL training tool

Level of difficulty Medium
Reading time 1 min
Views 883

Ссылка на русскую версию / link to Russian version

Understanding valid/ready protocol is extremely important for every microarchitect.

Valid/ready is one of the main protocols used to organise flow-control inside a logic block as well as on inter-block (SoC) level.

In the last lesson, we explored FIFO buffer using hdlgadgets - human-in-the-loop HDL training tool.

This time we will take two FIFO buffers (which form a pipeline with valid/ready handshakes) and will experiment with it by changing flow-control logic of the pipeline.

We will show that valid/ready is not only a mechanism for transferring data from one FIFO queue to another, but also a method for organizing various kinds of logical functionality between queues.

If you have not worked with valid/ready protocol before, you will be surprised how easy it is to achieve desired functionality of the design by simply writing couple of lines of Verilog code in the handshaking logic block between two FIFOs.

Read further and watch the video
Total votes 6: ↑6 and ↓0 +6
Comments 0

Exploring FIFO principles using an HDL training tool

Level of difficulty Medium
Reading time 1 min
Views 563

Ссылка на русскую версию / link to Russian version

FIFO is a key concept in hardware design. Understanding of FIFO is necessary for understanding the valid/ready protocol, which in turn is necessary for organisation of flow-control within a design.

Unfortunately, there are very few books on this topic, and to be fair, microarchitectural concepts are quite difficult to master from books, since understanding of these concepts are coming with practice. In other words it is more about developing hardware intuition.

The idea of the HDL training tool is that it can help develop a hardware intuition, providing the opportunity to explore ready-made scenarios in a step-by-step interactive way. The tool also provides detailed visualization of a simulated scenario.

Since the tool is a front-end for the HDL simulator, the real, synthesized SystemVerilog is executed on the simulator itself, which can be viewed and even modified.

So, the video of exploring FIFO on the training tool is here:

Watch the video and continue reading
Total votes 4: ↑4 and ↓0 +4
Comments 0

MemGame

Reading time 2 min
Views 1.2K

We are the first year students studying Computer Science in Innopolis University and we would like to share our experience in developing a Verilog program to create the greatest Memory Game (MemGame) that has ever existed on the FPGA board.

In this article, we decided to create a game for extending human memory. You will read the background theory and the incredible story of creation.

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Total votes 6: ↑6 and ↓0 +6
Comments 1

“FPGA InsideOut” – animation about CRC and parallel CRC calculation

Reading time 2 min
Views 1.4K

Ссылка на русскую версию / link to Russian version

FPGA InsideOut is an attempt to make a set of educational FPGA videos presented in the “human-in-the-loop” style. In these videos we will not only show how we are interfacing with an actual FPGA board but will also provide synchronous real-time visualisation of FPGA's internal logic.

For our first video we have picked a CRC circuit (cycle redundancy check) which is based on a linear feedback shift register. This circuit goes through several transformations during the course of the video. Intrigued? - let’s watch the video.

Watch the video and continue reading
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The Dino game from Google Chrome using FPGA

Reading time 4 min
Views 3.6K

Many people are familiar with the situation when there is no Internet, and a small dinosaur appears on the Google Chrome screen. Today we will tell you how to implement this game on the Cyclone IV FPGA board.

We are Yegor Blinov, Egor Kuziakov, and Inga Ezhova - the first-year students of Innopolis University. In our program, there was a course "Computer Architecture", where we had labs with FPGA boards Cyclone IV and MAX10. We were inspired by this equipment and decided to implement the project on one of the boards.

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Total votes 7: ↑7 and ↓0 +7
Comments 3

High-level pipelining in TL-Verilog, RISC-V from Imagination, formal tools and open-source EDA on ChipEXPO in Moscow

Reading time 3 min
Views 2.1K

This year ChipEXPO conference in Moscow invited several Western speakers to present in English the emerging technologies in high-level HDLs, formal verification, open-source EDA and using industrual RISC-V cores for education. You can join these presentations on September 14-16 for free using this link (you may need to use google translate from Russian to go through the registration) https://eventswallet.com/en/events/282/

The whole program is here

The English-speaking presentations and tutorials include:

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Total votes 3: ↑2 and ↓1 +1
Comments 2

System-on-Chip bus: AXI4 simplified and explained

Reading time 20 min
Views 25K

Protocol AXI4 was developed for High-bandwidth and low latency applications. It is designed to allow communication between master and slave devices. Master is typically a DMA or CPU and slaves are DRAM controllers, or other specific protocol controllers: UART, SPI, and others. Sometimes one component can implement multiple instances of this protocol. Usually, a prefix is used to differentiate between multiple AXI4 interfaces.

For example, Ethernet MAC can integrate DMA and slave interface used to command MAC. MAC can accept commands on the slave interface that contain data about the location of the next ethernet packet and MAC can start fetching this packet using the separate master interface instance.

This article was motivated by common design mistakes AXI4 designers make when they are designing their Digital IP. (Looking at you Xilinx)

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Total votes 10: ↑10 and ↓0 +10
Comments 1

Koyaanisqatsi: The WYSIWYG-style byte-code CPU

Reading time 5 min
Views 1.4K
Draft diagram of core

SVG-File (actual draft)

Lyrics


Ancient times are known to everyone not with immortal works from Homer's only, but also with the Pythagorean multiplication table, Euclidean geometry and the Archimedes screw and the Pi, which we learned to use only relatively recently. In antiquity the art was not only to be able to write poetry and prose, but to design catapults or battering tools also, now there are rigid frameworks, when the discovering the new another beautiful formula is a formal words play only.
Mathematics rules the modern world completely, cynically intertwining with the world of art, intruding with calculations in all spheres of our recreation and everyday life, when the colors of masterpieces turning into poisonous colours.
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Total votes 2: ↑2 and ↓0 +2
Comments 0

Passcode Data Protection by Using FPGA and Verilog

Reading time 4 min
Views 2.7K

There are many situations when you need to protect your data, and different tools can be used to do that. For example, a safe. We develop a passcode data protection mechanism by using an FPGA board and Quartus Prime software. It allows demonstrating the basic concepts of a combination lock such as entering data, setting and checking a passcode, and displaying data.

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Total votes 5: ↑3 and ↓2 +1
Comments 0
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