Last week I was doing a seminar on SystemVerilog, ASIC and FPGA at ADA University in Baku, Azerbaijan. I will replicate the last two sessions of this seminar, on RISC-V CPU simulation and synthesis, at the Verilog Meetups on March 3 and March 10 at Hacker Dojo, Mountain View, California. For this reason I am combining the information about Azerbaijan and California seminars in a single post.
First, let's talk about ADA University.
The team developing a set of portable SystemVerilog examples decided to organize the first event in Silicon Valley on Sunday, January 14 from 2PM till 5PM at Hacker Dojo in Mountain View, CA. If the first event is successful we are going to make it recurrent. You can register for the event on Meetup or LinkedIn.
The current directions of the group:
Ссылка на русскую версию / link to Russian version
Understanding valid/ready protocol is extremely important for every microarchitect.
Valid/ready is one of the main protocols used to organise flow-control inside a logic block as well as on inter-block (SoC) level.
In the last lesson, we explored FIFO buffer using hdlgadgets - human-in-the-loop HDL training tool.
This time we will take two FIFO buffers (which form a pipeline with valid/ready handshakes) and will experiment with it by changing flow-control logic of the pipeline.
We will show that valid/ready is not only a mechanism for transferring data from one FIFO queue to another, but also a method for organizing various kinds of logical functionality between queues.
If you have not worked with valid/ready protocol before, you will be surprised how easy it is to achieve desired functionality of the design by simply writing couple of lines of Verilog code in the handshaking logic block between two FIFOs.
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For the last 30 years digital chip design is not a schematic entry anymore: hardware engineers write code just like software engineers.
The difference is that the code software engineer writes becomes a chain of CPU instructions stored in memory, while the code in a hardware description language (HDL) becomes the CPU itself, its transistors and metal connections. And not only a CPU: the same technique is used to design processor-less ("fixed function") blocks in GPU that shuffle triangles and pixels, as well as network router chips that edit packet headers 100 times faster than CPU.
There are ways to experience this workflow without paying a million dollars to a silicon fab. One way is simulation, and another way is to use a matrix of reconfigurable logic cells, a Field Programmable Gate Array (FPGA). You can come on January 14 to Hacker Dojo in Mountain View, California. We have a bunch of computers and FPGA boards, and we will show you how to use them not only to blink LEDs but also to output graphics and recognize music.
This will change your perspective of what the code is.
Ссылка на русскую версию / link to Russian version
FIFO is a key concept in hardware design. Understanding of FIFO is necessary for understanding the valid/ready protocol, which in turn is necessary for organisation of flow-control within a design.
Unfortunately, there are very few books on this topic, and to be fair, microarchitectural concepts are quite difficult to master from books, since understanding of these concepts are coming with practice. In other words it is more about developing hardware intuition.
The idea of the HDL training tool is that it can help develop a hardware intuition, providing the opportunity to explore ready-made scenarios in a step-by-step interactive way. The tool also provides detailed visualization of a simulated scenario.
Since the tool is a front-end for the HDL simulator, the real, synthesized SystemVerilog is executed on the simulator itself, which can be viewed and even modified.
So, the video of exploring FIFO on the training tool is here:
Since the New Year we had 7 Verilog meetups at HackerDojo. We discussed the modern way of designing digital circuits using hardware description languages, the exercises on FPGA boards and the topic of microarchitecture. For the last two sessions we went over the most basic CPU core that can be used as a baseline for further exercises.
Now, in order to make progress toward the goal of creating new educational materials, it is essential for the regular participants to solve all the homework exercises (see the details in the post below) in parallel with studying the recommended materials.
The next steps are:
1) We are going to do weekly Zoom calls on Sundays, starting March 24, 2024 at 11 am California time (summer time). The link. During this call we are going to discuss the SystemVerilog Homework and the individual projects.
2) Once we develop more materials, we are going to organize a Show-and-Tell session in Hacker Dojo, for a wider audience. During the session several participants from the core team will present demos on various FPGA boards and explain to the curious how FPGA and ASIC work.
The first three meetups of the Portable SystemVerilog Examples group at Hacker Dojo in Mountain View, California were a kind of brainstorming sessions. We discussed the electronic industry, the essence of modern chip design, and the challenges to educate new design engineers. Now we are moving into a new mode of action. We are going to have weekly meetings of the core R&D team and monthly or bi-monthly events for a larger audience.
We are focusing on interview-level microarchitectural and CPU design examples, providing FPGA vendor-neutral infrastructure and compatibility with open-source ASIC design tools.
Need to start your career or hobby in digital design and verification of silicon chips or reconfigurable hardware? Explore multiple FPGA toolchains and open-source ASIC tools? Design your own RISC-V CPU or ML accelerator? Prepare for an interview in SystemVerilog? Come to our first Silicon Valley meetup on portable SystemVerilog examples for ASIC and FPGA.
