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Programming microcontrollers *

Learning how to program microcontrollers

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Bootstrapping Azerbaijan as a new center of ASIC design + Verilog Meetup #6 in Silicon Valley

Reading time 11 min
Views 781

Last week I was doing a seminar on SystemVerilog, ASIC and FPGA at ADA University in Baku, Azerbaijan. I will replicate the last two sessions of this seminar, on RISC-V CPU simulation and synthesis, at the Verilog Meetups on March 3 and March 10 at Hacker Dojo, Mountain View, California. For this reason I am combining the information about Azerbaijan and California seminars in a single post.

First, let's talk about ADA University.

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Total votes 6: ↑6 and ↓0 +6
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Verilog Meetups @ Hacker Dojo: the status and the plans for February 2024

Reading time 9 min
Views 1.2K

The first three meetups of the Portable SystemVerilog Examples group at Hacker Dojo in Mountain View, California were a kind of brainstorming sessions. We discussed the electronic industry, the essence of modern chip design, and the challenges to educate new design engineers. Now we are moving into a new mode of action. We are going to have weekly meetings of the core R&D team and monthly or bi-monthly events for a larger audience.

We are focusing on interview-level microarchitectural and CPU design examples, providing FPGA vendor-neutral infrastructure and compatibility with open-source ASIC design tools.

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Total votes 3: ↑3 and ↓0 +3
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Portable SystemVerilog Examples for ASIC and FPGA: the results of the meetup on 2024-01-21 and the next steps

Reading time 4 min
Views 1K

The second meetup of the Portable SystemVerilog Examples group on January 21 2024 at Hacker Dojo in Mountain View, California, went as planned: we moved from the stage of presenting the project to the self-introductions of the participants and the initial tutorial with the first examples. We also started distributing the tasks. The next meetup is tentatively scheduled for January 28 at the same location, from 2 pm to 5 pm. The contents of the meeting will be to work on the examples: basics-graphics-music and systemverilog-homework.

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Total votes 2: ↑1 and ↓1 0
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Why would a software engineer attend an FPGA hardware meetup at Hacker Dojo?

Reading time 6 min
Views 1K

For the last 30 years digital chip design is not a schematic entry anymore: hardware engineers write code just like software engineers.

The difference is that the code software engineer writes becomes a chain of CPU instructions stored in memory, while the code in a hardware description language (HDL) becomes the CPU itself, its transistors and metal connections. And not only a CPU: the same technique is used to design processor-less ("fixed function") blocks in GPU that shuffle triangles and pixels, as well as network router chips that edit packet headers 100 times faster than CPU.

There are ways to experience this workflow without paying a million dollars to a silicon fab. One way is simulation, and another way is to use a matrix of reconfigurable logic cells, a Field Programmable Gate Array (FPGA). You can come on January 14 to Hacker Dojo in Mountain View, California. We have a bunch of computers and FPGA boards, and we will show you how to use them not only to blink LEDs but also to output graphics and recognize music.

This will change your perspective of what the code is.

Prepare for a ride:
Total votes 8: ↑6 and ↓2 +4
Comments 0

Toward the January meetup on portable SystemVerilog examples in Silicon Valley

Reading time 4 min
Views 1K

The team developing a set of portable SystemVerilog examples decided to organize the first event in Silicon Valley on Sunday, January 14 from 2PM till 5PM at Hacker Dojo in Mountain View, CA. If the first event is successful we are going to make it recurrent. You can register for the event on Meetup or LinkedIn.

The current directions of the group:

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Total votes 10: ↑8 and ↓2 +6
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The first Silicon Valley meetup on portable SystemVerilog examples for ASIC and FPGA

Reading time 3 min
Views 892

Need to start your career or hobby in digital design and verification of silicon chips or reconfigurable hardware? Explore multiple FPGA toolchains and open-source ASIC tools? Design your own RISC-V CPU or ML accelerator? Prepare for an interview in SystemVerilog? Come to our first Silicon Valley meetup on portable SystemVerilog examples for ASIC and FPGA.

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Total votes 4: ↑3 and ↓1 +2
Comments 2

Exploring VALID/READY protocol, pipelines and experimenting with flow control using an HDL training tool

Level of difficulty Medium
Reading time 1 min
Views 878

Ссылка на русскую версию / link to Russian version

Understanding valid/ready protocol is extremely important for every microarchitect.

Valid/ready is one of the main protocols used to organise flow-control inside a logic block as well as on inter-block (SoC) level.

In the last lesson, we explored FIFO buffer using hdlgadgets - human-in-the-loop HDL training tool.

This time we will take two FIFO buffers (which form a pipeline with valid/ready handshakes) and will experiment with it by changing flow-control logic of the pipeline.

We will show that valid/ready is not only a mechanism for transferring data from one FIFO queue to another, but also a method for organizing various kinds of logical functionality between queues.

If you have not worked with valid/ready protocol before, you will be surprised how easy it is to achieve desired functionality of the design by simply writing couple of lines of Verilog code in the handshaking logic block between two FIFOs.

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Total votes 6: ↑6 and ↓0 +6
Comments 0

Exploring FIFO principles using an HDL training tool

Level of difficulty Medium
Reading time 1 min
Views 563

Ссылка на русскую версию / link to Russian version

FIFO is a key concept in hardware design. Understanding of FIFO is necessary for understanding the valid/ready protocol, which in turn is necessary for organisation of flow-control within a design.

Unfortunately, there are very few books on this topic, and to be fair, microarchitectural concepts are quite difficult to master from books, since understanding of these concepts are coming with practice. In other words it is more about developing hardware intuition.

The idea of the HDL training tool is that it can help develop a hardware intuition, providing the opportunity to explore ready-made scenarios in a step-by-step interactive way. The tool also provides detailed visualization of a simulated scenario.

Since the tool is a front-end for the HDL simulator, the real, synthesized SystemVerilog is executed on the simulator itself, which can be viewed and even modified.

So, the video of exploring FIFO on the training tool is here:

Watch the video and continue reading
Total votes 4: ↑4 and ↓0 +4
Comments 0

Setup of Qt Creator for programming and debugging of STM32 microcontrollers

Level of difficulty Medium
Reading time 9 min
Views 1.5K

Currently I am investigating firmware development for STM32 microcontrollers and I would like to share with you my experience for doing it in Qt Creator IDE.

There are a lot of IDEs, which are used for firmware development of STM32. Some of them, being quite comfortable, have restrictions for trial license. For example, the one of the most known IDE, IAR Embedded, suggests either a limited amount of product usage time (30 days) or the limited firmware size of 32 MB, which is not too much.

Within this scope of the publication, we investigate the method of setting up an environment that allows one to develop the full value of the STM32 firmware in Qt Creator.

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Working with digital infrared passive motion sensor PYD 1588

Reading time 10 min
Views 2.2K

In this article, there is the work with the PYD 1588 digital Infrared passive motion sensor introduced. The PYD 1588 is a serial opposed format, two element detector based on pyroceramic produced by the Excelitas Technologies. This sensor represents a low-power (3.0 uA with 1.8 V source voltage as in the documentation said) passive component with two sensible elements, which measure the thermal infrared radiation stream.

The signal is converted to a digital value using Sigma-Delta and DSP techniques. A configurable motion detection unit is implemented, which can generate an interrupt recognized by the external microcontroller (MCU) in case motion is detected. The motion detection unit contributes to significant device energy efficiency increasing via putting the MCU to a low-power sleep mode with no periodic raw data request and its analyzing necessity.

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Total votes 3: ↑3 and ↓0 +3
Comments 1

Alternate of Packed-Binary Time Format

Reading time 2 min
Views 2K

The Real-Time Clock (RTC) Calendar Registers in STM32 microcontrollers implemented in Binary Code Decimal format (BCD) i. e., every two digits are represented by one byte (low digit in 0-3 bits and high digit 4-7 bits). At least there are 5 bytes required to store date and time data in a such format. There are cases when memory allocation for time stamp might become critical, e. g., the events log keeping in an extern non-volatile memory IC. Here the memory value for a single event (event serial number, timestamp, event parameters, and its CRC) is fixed and can compose up to 16 bytes. The maximum quantity of the events increasing, and time spent on a single operation reducing (for reserved power sources as supercapacitors and electrolytic capacitors is critical) can be achieved with less memory amount required for the event field.

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“FPGA InsideOut” – animation about CRC and parallel CRC calculation

Reading time 2 min
Views 1.4K

Ссылка на русскую версию / link to Russian version

FPGA InsideOut is an attempt to make a set of educational FPGA videos presented in the “human-in-the-loop” style. In these videos we will not only show how we are interfacing with an actual FPGA board but will also provide synchronous real-time visualisation of FPGA's internal logic.

For our first video we have picked a CRC circuit (cycle redundancy check) which is based on a linear feedback shift register. This circuit goes through several transformations during the course of the video. Intrigued? - let’s watch the video.

Watch the video and continue reading
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PVS-Studio checks the code of Flipper Zero dolphin

Reading time 12 min
Views 1.6K

Flipper Zero + PVS-Studio


Flipper Zero is an open-source multi-tool for geeks and penetration testers. It so happened that the Flipper Zero project and the PVS-Studio analyzer crossed paths. A philosophical question: should we check the project, if the project developers have already started fixing errors? Let's try to do this.

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Total votes 6: ↑5 and ↓1 +4
Comments 0

On the recent vulnerability in Diebold Nixdorf ATMs

Reading time 8 min
Views 3.9K

Hi there! A while ago, Positive Technologies published the news that ATMs manufactured by Diebold Nixdorf (previously known as Wincor), or more specifically, the RM3 and CMDv5 cash dispensers, contained a vulnerability which allowed attackers to withdraw cash and upload modified (vulnerable) firmware. And since my former colleague Alexei Stennikov and I were directly involved in finding this vulnerability, I would like to share some details.

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Total votes 5: ↑5 and ↓0 +5
Comments 2

MISRA C: struggle for code quality and security

Reading time 11 min
Views 1.2K

A couple of years ago the PVS-Studio analyzer got its first diagnostic rules to check program code compliance with the MISRA C and MISRA C++ standards. We collected feedback and saw that our clients were interested in using the analyzer to check their projects for MISRA compliance. So, we decided to further develop the analyzer in this direction. The article covers the MISRA C/C++ standard and the MISRA Compliance report. It also shows what we already managed to do and what we plan to achieve by the end of the year.


0866_MISRA_C/image1.png

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High-level pipelining in TL-Verilog, RISC-V from Imagination, formal tools and open-source EDA on ChipEXPO in Moscow

Reading time 3 min
Views 2.1K

This year ChipEXPO conference in Moscow invited several Western speakers to present in English the emerging technologies in high-level HDLs, formal verification, open-source EDA and using industrual RISC-V cores for education. You can join these presentations on September 14-16 for free using this link (you may need to use google translate from Russian to go through the registration) https://eventswallet.com/en/events/282/

The whole program is here

The English-speaking presentations and tutorials include:

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Total votes 3: ↑2 and ↓1 +1
Comments 2

UAVCAN HITL UAV Simulator for PX4

Reading time 2 min
Views 2.5K

Hi from RaccoonLab, a team of enthusiasts in field robotics! We want to share our true-HITL UAVCAN-based simulator for PX4.

We believe a unified UAVCAN bus for drone onboard electronics will become a mainstream approach shortly. Our simulator is already based on UAVCAN (in opposition to UART-MAVLINK) and emulates exactly the same messages as real UAVCAN-sensors.

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Total votes 2: ↑2 and ↓0 +2
Comments 0

Why do you need the MISRA Compliance report and how to generate one in PVS-Studio?

Reading time 5 min
Views 828

If you are strongly interested in MISRA and would like to understand whether your project meets one of the MISRA association's standards, there is a solution. It's name is MISRA Compliance. PVS-Studio has recently learned how to generate the MISRA Compliance report. This article describes how you can use this feature. This can make somebody's life better.

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