Programming microcontrollers *

Gowin has clear advantages over Xilinx in the educational FPGA board market: Gowin boards are several times less expensive, the synthesis speed is several times faster, and the EDA package is two orders of magnitude smaller: we are talking about 1G versus 100G disk space. Of course, Xilinx is still the king of high-end prototyping boards that cost $10K-100K, but for the students such boards are irrelevant; such boards are for ASIC design companies. A beginning EE student needs a board for less than $100, and Gowin not only fits the bill but also covers all the needs, specifically:

Hello my name is Dmitry. Recently I wrote article "Building firmware for Orange PI i96 (Orange PI 2g-iot) from scratch" . If you haven't read it yat, I highly recommend. And there I noticed that in order to build firware on current kernel, I have to rewrite drivers wirh new archetecture "Device tree". In this article I have revelate how I do it.

Hellow my name is Dmitry. Once I bought "Orange PI i96", but unfortunately producer not update it firmvere very long. Last firmwere kernel version is 3.10.62 but kernel current at time this article writing (russian version) is 6.5.1. And so I decide build my own firmware from scratch, and do it from sourse completely.

Since the New Year we had 7 Verilog meetups at HackerDojo. We discussed the modern way of designing digital circuits using hardware description languages, the exercises on FPGA boards and the topic of microarchitecture. For the last two sessions we went over the most basic CPU core that can be used as a baseline for further exercises.

Now, in order to make progress toward the goal of creating new educational materials, it is essential for the regular participants to solve all the homework exercises (see the details in the post below) in parallel with studying the recommended materials.

The next steps are:

1) We are going to do weekly Zoom calls on Sundays, starting March 24, 2024 at 11 am California time (summer time). The link. During this call we are going to discuss the SystemVerilog Homework and the individual projects.

2) Once we develop more materials, we are going to organize a Show-and-Tell session in Hacker Dojo, for a wider audience. During the session several participants from the core team will present demos on various FPGA boards and explain to the curious how FPGA and ASIC work.

Last week I was doing a seminar on SystemVerilog, ASIC and FPGA at ADA University in Baku, Azerbaijan. I will replicate the last two sessions of this seminar, on RISC-V CPU simulation and synthesis, at the Verilog Meetups on March 3 and March 10 at Hacker Dojo, Mountain View, California. For this reason I am combining the information about Azerbaijan and California seminars in a single post.

First, let's talk about ADA University.

The first meetups of the Portable SystemVerilog Examples group at Hacker Dojo in Mountain View, California were a kind of brainstorming sessions. We discussed the electronic industry, the essence of modern chip design, and the challenges of educating new design engineers. Then we moved to a new mode of action. We started weekly meetings of the core R&D team with the goal to prepare educational materials for the events for a larger audience. The meetings are generally held on Sundays from 11 pm to 2 pm. If you cannot come to Mountain View, you can join online.

We are focusing on interview-level microarchitectural and CPU design examples, providing FPGA vendor-neutral infrastructure and compatibility with open-source ASIC design tools.

The second meetup of the Portable SystemVerilog Examples group on January 21 2024 at Hacker Dojo in Mountain View, California, went as planned: we moved from the stage of presenting the project to the self-introductions of the participants and the initial tutorial with the first examples. We also started distributing the tasks. The next meetup is tentatively scheduled for January 28 at the same location, from 2 pm to 5 pm. The contents of the meeting will be to work on the examples: basics-graphics-music and systemverilog-homework.

For the last 30 years digital chip design is not a schematic entry anymore: hardware engineers write code just like software engineers.

The difference is that the code software engineer writes becomes a chain of CPU instructions stored in memory, while the code in a hardware description language (HDL) becomes the CPU itself, its transistors and metal connections. And not only a CPU: the same technique is used to design processor-less ("fixed function") blocks in GPU that shuffle triangles and pixels, as well as network router chips that edit packet headers 100 times faster than CPU.

There are ways to experience this workflow without paying a million dollars to a silicon fab. One way is simulation, and another way is to use a matrix of reconfigurable logic cells, a Field Programmable Gate Array (FPGA). You can come on January 14 to Hacker Dojo in Mountain View, California. We have a bunch of computers and FPGA boards, and we will show you how to use them not only to blink LEDs but also to output graphics and recognize music.

This will change your perspective of what the code is.

The team developing a set of portable SystemVerilog examples decided to organize the first event in Silicon Valley on Sunday, January 14 from 2PM till 5PM at Hacker Dojo in Mountain View, CA. If the first event is successful we are going to make it recurrent. You can register for the event on Meetup or LinkedIn.

The current directions of the group:

Need to start your career or hobby in digital design and verification of silicon chips or reconfigurable hardware? Explore multiple FPGA toolchains and open-source ASIC tools? Design your own RISC-V CPU or ML accelerator? Prepare for an interview in SystemVerilog? Come to our first Silicon Valley meetup on portable SystemVerilog examples for ASIC and FPGA.

Ссылка на русскую версию / link to Russian version

Understanding valid/ready protocol is extremely important for every microarchitect.

Valid/ready is one of the main protocols used to organise flow-control inside a logic block as well as on inter-block (SoC) level.

In the last lesson, we explored FIFO buffer using hdlgadgets - human-in-the-loop HDL training tool.

This time we will take two FIFO buffers (which form a pipeline with valid/ready handshakes) and will experiment with it by changing flow-control logic of the pipeline.

We will show that valid/ready is not only a mechanism for transferring data from one FIFO queue to another, but also a method for organizing various kinds of logical functionality between queues.

If you have not worked with valid/ready protocol before, you will be surprised how easy it is to achieve desired functionality of the design by simply writing couple of lines of Verilog code in the handshaking logic block between two FIFOs.

Ссылка на русскую версию / link to Russian version

FIFO is a key concept in hardware design. Understanding of FIFO is necessary for understanding the valid/ready protocol, which in turn is necessary for organisation of flow-control within a design.

Unfortunately, there are very few books on this topic, and to be fair, microarchitectural concepts are quite difficult to master from books, since understanding of these concepts are coming with practice. In other words it is more about developing hardware intuition.

The idea of the HDL training tool is that it can help develop a hardware intuition, providing the opportunity to explore ready-made scenarios in a step-by-step interactive way. The tool also provides detailed visualization of a simulated scenario.

Since the tool is a front-end for the HDL simulator, the real, synthesized SystemVerilog is executed on the simulator itself, which can be viewed and even modified.

So, the video of exploring FIFO on the training tool is here:

Currently I am investigating firmware development for STM32 microcontrollers and I would like to share with you my experience for doing it in Qt Creator IDE.

There are a lot of IDEs, which are used for firmware development of STM32. Some of them, being quite comfortable, have restrictions for trial license. For example, the one of the most known IDE, IAR Embedded, suggests either a limited amount of product usage time (30 days) or the limited firmware size of 32 MB, which is not too much.

Within this scope of the publication, we investigate the method of setting up an environment that allows one to develop the full value of the STM32 firmware in Qt Creator.

In this article I will talk about my attempt to create flexible, compact and beautiful modular prototyping framework

In this article, there is the work with the PYD 1588 digital Infrared passive motion sensor introduced. The PYD 1588 is a serial opposed format, two element detector based on pyroceramic produced by the Excelitas Technologies. This sensor represents a low-power (3.0 uA with 1.8 V source voltage as in the documentation said) passive component with two sensible elements, which measure the thermal infrared radiation stream.

The signal is converted to a digital value using Sigma-Delta and DSP techniques. A configurable motion detection unit is implemented, which can generate an interrupt recognized by the external microcontroller (MCU) in case motion is detected. The motion detection unit contributes to significant device energy efficiency increasing via putting the MCU to a low-power sleep mode with no periodic raw data request and its analyzing necessity.

The Real-Time Clock (RTC) Calendar Registers in STM32 microcontrollers implemented in Binary Code Decimal format (BCD) i. e., every two digits are represented by one byte (low digit in 0-3 bits and high digit 4-7 bits). At least there are 5 bytes required to store date and time data in a such format. There are cases when memory allocation for time stamp might become critical, e. g., the events log keeping in an extern non-volatile memory IC. Here the memory value for a single event (event serial number, timestamp, event parameters, and its CRC) is fixed and can compose up to 16 bytes. The maximum quantity of the events increasing, and time spent on a single operation reducing (for reserved power sources as supercapacitors and electrolytic capacitors is critical) can be achieved with less memory amount required for the event field.

Ссылка на русскую версию / link to Russian version

FPGA InsideOut is an attempt to make a set of educational FPGA videos presented in the “human-in-the-loop” style. In these videos we will not only show how we are interfacing with an actual FPGA board but will also provide synchronous real-time visualisation of FPGA's internal logic.

For our first video we have picked a CRC circuit (cycle redundancy check) which is based on a linear feedback shift register. This circuit goes through several transformations during the course of the video. Intrigued? - let’s watch the video.

Flipper Zero is an open-source multi-tool for geeks and penetration testers. It so happened that the Flipper Zero project and the PVS-Studio analyzer crossed paths. A philosophical question: should we check the project, if the project developers have already started fixing errors? Let's try to do this.

Demid Efremov and Ivan Kornienko.

Music box on Verilog HDL for Cyclone IV.

Hi there! A while ago, Positive Technologies published the news that ATMs manufactured by Diebold Nixdorf (previously known as Wincor), or more specifically, the RM3 and CMDv5 cash dispensers, contained a vulnerability which allowed attackers to withdraw cash and upload modified (vulnerable) firmware. And since my former colleague Alexei Stennikov and I were directly involved in finding this vulnerability, I would like to share some details.