Here is my take on Verilog-vs-VHDL
In the early 1990s many people thought that Verilog was a temporary language and was going away with VHDL standard adoption.
At the same time, many people complained that VHDL has different incompatible arithmetic packages (numeric_std and std_logic_arith) and writing something like
wire [3:0] a, b;
wire [4:0] c = a + b;
becomes something like
signal a, b : std_logic_vector (3 downto 0);
signal c : std_logic_vector (4 downto 0);
c <= std_logic_vector (resize (unsigned (a), 5) + resize (unsigned (b), 5))
Finally John Cooley, the first blogger of EDA industry (he started his blog http://deepchip.com even before the word "blogger" appeared in the press) decided to make a hackathon in 1997 (at that moment the word "hackathon" was also unknown) to find out who is more productive - Verilog or VHDL engineers.
John Cooley published the results in an article
"The Unexpected Results From A Hardware Design Contest: Verilog Won & VHDL Lost? -- You Be The Judge!"
https://www.angelfire.com/in/rajesh52/contest.html
He found that the Verilog engineers were more productive in his challenge.
After that more and more companies started to switch to Verilog, especially when Verilog-2001 and SystemVerilog integrated all the features of VHDL (packages, generate, records/structs etc).
In the early 2000s Synopsys developers thought that VHDL was going to die soon. However they continued to maintain VHDL support for die-hard VHDL users like Texas Instruments, IBM and the military. But even the Pentagon eventually back in 2008 allowed contractors to mix VHDL RTL designs with SystemVerilog testbenches (before they used a mix of VHDL and Specman e language).
However, VHDL at some moment stopped declining and stabilized. For example PowerVR GPU used in Apple iPhone 1-4 was written in VHDL by the British company Imagination. VHDL is still used but EDA companies give SystemVerilog priority when implementing language support in their tools.
